Computer Organization
Q141.
A 32-bit wide main memory unit with a capacity of 1 GB is built using 256M x 4-bit DRAM chips. The number of rows of memory cells in the DRAM chip is 2^{14}. The time taken to perform one refresh operation is 50 nanoseconds. The refresh period is 2 milliseconds. The percentage (rounded to the closest integer) of the time available for performing the memory read/write operations in the main memory unit is __________.Q142.
Suppose you want to build a memory with 4 byte words and a capacity of 2^{21} bits. What is type of decoder required if the memory is built using 2K \times 8 RAM chips?Q143.
If each address space represents one byte of storage space, how many address lines are needed to access RAM chips arranged in a 4 \times 6 array, where each chip is 8K \times 4 bits ?Q145.
A dynamic RAM has a memory cycle time of 64 nsec. It has to be refreshed 100 times per msec and each refresh takes 100 nsec. What percentage of the memory cycle time is used for refreshing?Q146.
The process of organizing the memory into two banks to allow 8-and 16-bit data operation is calledQ147.
A RAM chip has a capacity of 1024 words of 8 bits each (1K x 8). The number of 2 x 4 decoders with enable line needed to construct a 16K x 16 RAM from 1K x 8 RAM isQ150.
What is the minimum size of ROM required to store the complete truth table of an 8-bit \times 8-bit multiplier?